1. Field of the Invention
The present invention relates to a signal generating circuit including a delay-locked loop, to a driving device for a solid-state imaging device, the driving device including the signal generating circuit, and to an image capturing apparatus including the signal generating circuit.
2. Description of the Related Art
Recently, in order to improve the performance of various types of electronic equipment, such electronic equipment has included a plurality of semiconductor devices combined in a complex manner. Also, the plurality of semiconductor devices has been operated in synchronization with each other at a predetermined timing.
For example, in image capturing apparatuses, such as digital cameras and video cameras, a solid-state imaging device, a signal-processing device, a memory device, and the like are operated in synchronization with each other at a predetermined timing using a driving device.
In order to operate a plurality of semiconductor devices at a predetermined timing, known electronic equipment includes a signal generating circuit for generating a signal that changes at the predetermined timing.
A signal generating circuit for generating an output signal that changes at a predetermined timing using a delay-locked loop (hereinafter, referred to as a DLL) for generating a plurality of delay signals obtained by delaying a reference signal by predetermined time intervals and an arithmetic circuit prepared in advance is known (for example, see PCT Japanese Translation Patent Publication No. 6-500673).
The signal generating circuit having such an arrangement generates the output signal that changes at the predetermined timing by causing the arithmetic circuit to perform predetermined arithmetic processing on some delay signals from among the plurality of delay signals generated by the DLL.
In the known signal generating circuit described above, the use of the arithmetic circuit installed in the signal generating circuit in advance allows generation of an output signal that changes at a predetermined timing from delay signals generated by the DLL. Thus, only an output signal that changes at fixed rise time and fall time is generated. Therefore, an output signal that changes at a desired timing cannot be generated.
Consequently, the known signal generating circuit cannot generate signals that change at various timings used for various types of electronic equipment. Thus, the known signal generating circuit lacks of versatility.
Also, in the known signal generating circuit, in order to generate a signal that changes at a timing suitable for the equipment used, it is necessary to design an arithmetic circuit again. Thus, a great deal of time and effort is required for the development of signal generating circuits.